`timescale 1ns / 1ps

module CPU_tb;

	reg clk;
	reg reset;

	CPU cpu (
		.clk(clk), 
		.reset(reset)
	);

	always #1 clk = ~clk;

	initial begin
		clk = 0;
		reset = 1;

		#4;
		reset = 0;
        #1000;
		$finish;
	end
      
endmodule

